Image sensors play a role in transforming optical images to electrical signals. The image sensors are classified into two major categories, including a complementary metal-oxide-silicon (CMOS) image sensor and a charge coupled device (CCD) image sensor. The CCD image sensor has sensitivity and noise characteristics that are superior to the CMOS image sensor, but has disadvantages which include difficulty of high integration and high power dissipation. The CMOS image sensor has advantages which include simple fabrication, suitability for high integration and low power dissipation.
Recently, there have been improvements in fabrication of CMOS devices and the characteristics thereof. Moreover, extensive studies on the CMOS image sensor have been performed.
Conventionally, a pixel of the CMOS image sensor comprises a photodiode for receiving light and CMOS devices that control the image signals received from the photodiode.
FIG. 1 is a diagram illustrating a circuit of a CMOS image sensor.
Referring to FIG. 1, the CMOS image sensor includes a photodiode PD, a transfer transistor TT, a reset transistor TR, a selection transistor TS and an access transistor TA. The transfer transistor TT and the reset transistor TR are connected in serial with the photodiode PD. An applied voltage Vdd is supplied to a drain of the reset transistor TR. A drain of the transfer transistor TT (i.e., a source of the reset transistor TR) corresponds to the floating diffusion layer F/D. The floating diffusion layer F/D is connected to a gate of the selection transistor TS. The selection transistor TS and the access transistor TA are connected in serial and an applied voltage Vdd is supplied to a drain of the selection transistor TS. A gate of the access transistor TA is connected to an input port Pi. A source of the access transistor TA is connected to an output port Po.
In operation, the reset transistor TR is turned on to supply the applied voltage Vdd to the floating diffusion layer F/D and then the reset transistor TR is turned off. Thus, a predetermined voltage is applied to the floating diffusion layer F/D and the gate of the selection transistor TS. As a result, the source of the selection transistor TS reaches a predetermined voltage. This is a reset state.
In the reset state, if light is incident upon the photodiode PD, electron-hole pairs (EHPs) are generated and signal electrons are accumulated in the photodiode PD. Then the transfer transistor TT is turned on. As a result, the accumulated signal electrons are transferred to the floating diffusion layer F/D, which changes the voltage of the floating diffusion layer F/D. Therefore, the gate voltage of the selection transistor TS changes and the voltage applied to the source of the selection transistor TS also varies. Depending on the access signal that is applied to the input port Pi, data is generated at the output port Po. After outputting the data, the image sensor is returned to the reset state. By repeating these steps, image signals can be generated.
Some of the sources/drains of the transistors TT, TR, TS, and TA may include a metal silicide layer formed on surfaces thereof so as to reduce ohmic contact or resistance.
FIG. 2 is a schematic cross-sectional view showing a conventional CMOS image sensor. In the drawings, reference indications “a” and “b” refer to a light receiving region and a CMOS device region, respectively.
Referring to FIG. 2, a device isolation layer 2 is formed in a p-type semiconductor substrate 1 with the light receiving region “a” and the CMOS device region “b” so as to define an active region. The light receiving region “a” is the region where a photodiode PD is formed and the CMOS device region “b” is the region where the CMOS devices are formed. A gate oxide layer 3 and a gate electrode layer 4 are sequentially formed on an entire surface of the semiconductor substrate 1 with the device isolation layer 2. Then the gate electrode layer 4 and the gate oxide layer 3 are successively patterned to form a gate pattern 5. The gate pattern 5 is formed at the CMOS device region “b” and comprises a gate oxide layer 3 and a gate electrode layer 4 that are stacked.
An n-type photodiode 6 is formed at the diode region (i.e., an active region that includes the light receiving region “a”). A P-type photodiode 7 is formed between the n-type photodiode 6 and a top surface of the diode region.
Lightly doped impurity diffusion-layers 8 are formed in the active region on both sides of the gate pattern 5. A spacer layer 9 is formed on an entire surface of the substrate 1 with the lightly doped impurity diffusion layers 8. The spacer layer 9 is selectively and anisotropically etched to form spacers 9a at both sides of the gate pattern 5. The spacer layer 9 is positioned above the photodiodes 6 and 7.
Heavily doped impurity diffusion layers 8a are formed in the active region on the sides of the lightly doped impurity diffusion layers 8. A metal layer 10 is formed on an entire surface of the substrate 1 with the heavily doped impurity diffusion layers 8a. Silicon or polysilicon is reacted with the metal layer 10 to form a metal silicide layer 10a. The metal silicide layer 10a is selectively formed on a surface of the heavily doped impurity diffusion layers 8a. That is, the spacer layer 9 positioned above the photodiodes 6 and 7 prevents the silicide layer 10a from being formed on top of the photodiodes 6 and 7.
During the silicidation process, the metal layer 10 remains on top of the photodiodes 6 and 7. As a result, metal elements of the metal layer 10 penetrate the spacer layer 9 into the photodiodes 6 and 7. These penetrating metal elements may increase dark current of the photodiodes 6 and 7. Dark current means the current that flows from the pixels without light being incident upon the photodiodes 6 and 7. The dark current may increase the occurrence of dark defects that result when pixels operate without light.